1. Field of the Invention
The present invention relates to a method, a system, and a program for designing a power converter. In particular, the present invention relates to a semiconductor-device-loss designing method necessary for a design which increases the output power densities of power converters.
2. Description of the Related Art
Modern society depends on the premise that electrical power can be converted to a voltage, current, frequency, and phase suitable for use thereof, and electrical power can be freely used anywhere and anytime in any field of the society. Therefore, power converters, such as inverters, are used in a wide range of fields; for example, in information and telecommunication equipment, home appliances, industrial equipment, electrical railroads, power distribution systems, and power systems. With progress of power converter technologies, power converters have been reduced in size and weight. In association of this trend, the output power densities of power converters have been increased one-hundred hold or more in the past 30 years, and at present, an output power density of 5 W/cm3 is realized. Increasing the output power density will become more and more important in the future. The output power densities of power converters, which are used in power supplies of information and telecommunication systems, electric vehicles, and distributed power supplies of wind power generation systems and photovoltaic power generation systems, are considered to increase more and more.
In order to increase the output power density of a power converter, the volume of the converter must be reduced without lowering output power. Main components which determine the volume of a converter are a cooling unit and a filter. In order to reduce the volume of the cooling unit, it is important to perform thermal design in consideration of losses of semiconductor devices and a filter used in the power converter. Further, in order to reduce the volume of the filter, which is composed of an inductor and a capacitor, the switching frequency of the semiconductor devices must be increased.
An increase in the power density of a power converter is achieved through reduction of its volume. This volume reduction has been achieved by two fundamental methods; i.e., (1) reducing loss of a power converter to thereby reduce the volume of a cooling unit, and (2) increasing switching frequency to thereby reduce the volume of passive components such as an LC filter.
In order to reduce loss and simultaneously increase switching frequency, switching loss generated as a result of switching of semiconductor devices must be reduced. For such a purpose, the switching time must be shortened; that is, voltage change rate dv/dt and current change rate di/dt at the time of switching must be increased.
In order to reduce the sizes of a cooling unit and passive components to a theoretical limit while securing required functions of a power converter, loss of semiconductor devices, which becomes necessary when these unit and components are designed, must be accurately designed. Parameters associated with the main circuit of a power converter include true circuit parameters such as resistance R, inductance L, and capacitance C, which are provided so as to realize a predetermined circuit operation, and extrinsic circuit parameters such as parasitic inductance Ls and parasitic capacitance Cs, which are naturally generated in association with realizing a wiring structure that constitutes the main circuit. At time of switching, induced voltage Ls·di/dt stemming from the parasitic inductance Ls and displacement current Cs·dv/dt stemming from the parasitic capacitance Cs affect the voltage applied to the switched semiconductor devices and current flowing therethrough. Consequently, the parasitic inductance and the parasitic capacitance influence the loss of the semiconductor devices.
Accordingly, an accurate semiconductor-device-loss design method in which the influence of parasitic inductances and parasitic capacitances on the loss of semiconductor devices are taken into consideration is needed for design of a power converter of high power density. In a conventionally known semiconductor-device-loss design method, voltage applied to a semiconductor device and current flowing therethrough are calculated by use of a circuit simulator, and the product thereof is integrated with respect to time so as to calculate the loss of the semiconductor device (see Non-Patent Document 1).
However, in the circuit simulator, a semiconductor device is represented in the form of an equivalent circuit by use of electrical circuit elements such as a voltage source, a current source, an inductor, a capacitor, a resistor, etc. Therefore, the switching behavior of a semiconductor device, which is determined by non-linear semiconductor device parameters, and interaction between the semiconductor device parameters and the parasitic inductance and parasitic capacitance of the circuit cannot be represented completely on the simulator. Accordingly, accurately and quantitatively designing the loss of the semiconductor device is difficult.
In the method of calculating the loss by integrating the product of voltage and current at the time of switching, the loss cannot be separated to a component attributable to the semiconductor device and a component attributable to circuit parasitic parameters. Since the ratio of the loss attributable to the circuit parasitic parameters to the entire loss cannot be known, difficulty encounters in designing the circuit parasitic parameters which minimize the semiconductor device loss.
The loss of a power converter mainly consists of semiconductor device loss (about 60%), filter loss (about 30%), and other losses (about 10%) (see Non-Patent Document 2). In the conventional thermal design method for power converters, only thermal design for semiconductor devices whose loss accounts for a large portion of the entire loss is performed, and comprehensive thermal design in which filter loss and other losses are taken into consideration is not performed.
Parameters of the main circuit of a power converter include true circuit parameters such as resistance R, inductance L, and capacitance C, which are provided so as to realize a predetermined circuit operation, and extrinsic circuit parameters such as parasitic inductance Ls and parasitic capacitance Cs, which are naturally generated in association with realizing a wiring structure that constitutes the main circuit. In conventional power converters which are driven at a relatively low switching frequency of several kHz to several 10 kHz, the loss produced as a result of energy being charged into the parasitic inductance Ls and the parasitic capacitance Cs and discharged therefrom is small as compared with the loss of semiconductor devices and a filter, and therefore has been ignored.
Further, in conventional noise design for power converters which are driven at a relatively low switching frequency of several kHz to several 10 kHz, noise design is performed only for the switching frequency determined by the control system, and resonance frequency components generated by the parasitic inductance Ls and the parasitic capacitance Cs, which are extrinsic parameters associated with the main circuit of the converter, and deterioration of filter frequency characteristics attributable to a parasitic inductance Lfs and a parasitic capacitance Cfs, which are naturally generated when the wiring structure of the filter is realized, have been ignored.
FIG. 34 is a flowchart showing a typical conventional power converter design method. The conventional power converter design method is performed as follows.
In Step 1 for determination of target specifications, a rated capacity, a rated voltage, a rated current, a target efficiency, and a target power density of the power converter are determined.
In Step 2 for designing devices and the main circuit, a device which satisfies the rated voltage and current of the power converter is selected, and an on-resistance Ron, which is a semiconductor device parameter that determines conduction loss, is determined through (1) use of a data sheet of the semiconductor device or (2) measurement.
The on resistance Ron of the semiconductor device is substituted in the following Eq. (1) to thereby calculate the conduction loss Pcond.
                              P          COND                =                                                            VtI                d                                            π                ⁢                                  2                                                      ⁡                          [                              1                +                                                      1                    4                                    ⁢                  k                  ⁢                                                                          ⁢                  cos                  ⁢                                                                          ⁢                  ϕ                                            ]                                +                                                                      R                  ON                                ⁢                                  I                  d                  2                                                            2                ⁢                π                                      ⁡                          [                                                π                  2                                +                                                      4                    3                                    ⁢                  k                  ⁢                                                                          ⁢                  cos                  ⁢                                                                          ⁢                  ϕ                                            ]                                                          (        1        )            In Eq. (1), Vt represents the threshold voltage of the semiconductor device, and I represents the rms value of current flowing from the power converter to a load. k represents an amplitude modulation ratio used for controlling the amplitude of output voltage of the power converter, and cosφ represents the power factor of the load.
Further, turn-on switching energy EON(Iave) and turn-off switching energy EOFF(Iave) are experimentally. Iave represents the average value of current flowing through the semiconductor device, and can be given by the following equation by use of load current RMS value IRMS obtained from the target specifications.
                              I          ave                =                              2            π                    ⁢                      2                    ⁢                      I            RMS                                              (        2        )            
Next, in Step 3 for control/drive design, a switching frequency fSW and a switching pattern are determined as operation conditions for driving the power converter. The switching loss PSW of the semiconductor device is then obtained by use of the following equation.
                              P          SW                =                                            f              SW                        2                    ⁡                      [                                                            E                  Ton                                ⁡                                  (                                      I                    ave                                    )                                            +                                                E                  Toff                                ⁡                                  (                                      I                    ave                                    )                                                      ]                                              (        3        )            
The total loss of the semiconductor device is calculated by adding the above-described conduction loss PCOND and the switching loss PSW.
Next, in Step 4 for filter design, a filter inductance Lf and a filter capacitance Cf for removing harmonics of the switching frequency component from the output waveform of the converter are determined. The filter attenuation characteristic is determined from the filter inductance and the filter capacitance, which are generally set so that the attenuation factor becomes ⅕ to 1/10 at the switching frequency.
In Step 5, the power converter is manufactured on a trial basis by use of the results obtained in the above-described steps.
In Step 6, the target specifications of the power converter manufactured in Step 5 (e.g., conversion efficiency, power density, and temperature of the semiconductor device) are experimentally measured.
In Step 7, the specifications of the manufactured power converter are compared with the target specifications. If the target specifications are attained, the designing procedure is ended. If the target specifications are not attained, analysis and determination of adjustment parameters are performed in Step 8.
In Step 8 for analysis and determination of adjustment parameters, parameters which must be adjusted so as to attain the target specifications are determined. If the temperature of the semiconductor device is higher than an allowable operating temperature obtained from the data sheet, Step 2 for device/main circuit design or Step 3 for filter design is executed again. If the harmonics of the switching frequency component contained in the converter output waveform do not meet the specifications, Step 4 for filter design is executed again.
In small-sized, lightweight power converters of large output power density, such as CPU power supplies, power supplies for information and telecommunication systems such as data centers, and motor drivers of hybrid vehicles and fuel-cell vehicles, which are expected to grow in the future, super-low-loss semiconductor devices which can be switched at high speed will be used. In such a power converter having a high output power density, there must be considered the influence of extrinsic parameters such as parasitic inductance and parasitic capacitance on the losses of the semiconductor device and the filter, along with the required frequency characteristic. However, the conventional power converter design method having been described with reference to FIG. 34 cannot cope with such a problem.
In future power converters having high output power density and driven through high speed switching, there cannot be ignored the influence of semiconductor device loss attributable to interaction with the parasitic inductance and the parasitic capacitance stemming from the structure of the semiconductor device and the wiring structure of the power converter, which influence has been ignored in the past. Therefore, accurate thermal design cannot be performed by the conventional method.
The filter loss attributable to the parasitic inductance and the parasitic capacitance, and the required frequency characteristic will become factors which cannot be ignored. When the operation speed and frequency of the power conversion circuit are increased, an increase is seen in the influence of the resonance frequency component produced by the parasitic inductance and the parasitic capacitance, which influence has conventionally not been taken in consideration when the frequency characteristic of the filter is designed. Therefore, it becomes necessary to design a filter wiring structure and a filter structure for eliminating not only the switching frequency component but also the resonance frequency component. Further, since an increase is seen in the ratio of loss of a passive filter, which conventionally has not be taken into consideration in the designing step, to the overall loss of the converter, in addition to a method of designing semiconductor device loss, a method of designing passive-filter loss becomes necessary.
As described above, in the conventional power converter design method, the influence of parasitic inductance and parasitic capacitance, which become marked as a result of an increase in operation speed and frequency, is not quantified, and the target specifications are attained through repetition of fine adjustment accompanied by trial manufacture and re-design. Therefore, when a power converter which operates at high speed and high frequency at which the influence of parasitic inductance and parasitic capacitance becomes remarkable is designed, a huge amount of time is required for trial manufacture and re-resign. Further, a converter cannot be optimally designed by the design method in which the target specifications are attained through repetition of trial manufacture and re-design.
[Non Patent Document 1] Z. Liang, B. Lu, J. D. van Wyk and F. C. Lee, IEEE trans. on Power Electronics, Vol. 20, No. 3(2005).
[Non Patent Document 2] A. Lidow, Proc. of IEEE, 89, 803(2001).